1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns methods of testing multi-chip electronic modules.
2. Description of the Related Art
Semiconductor manufacturers continually strive to increase the packaging density of integrated circuit chips, which has led to the development of high-density electronic packaging modules such as three-dimensional multi-chip structures. Multi-chip structures typically comprise a plurality of integrated circuit chips that are adhered together in a stack so as to reduce the amount of space that the chips occupy inside a system. Typically, each chip in the stack has a plurality of conductive input/output contacts that are exposed on at least one lateral surface of the chip. The exposed contacts provide conductive interconnection between the chips in the stack and external circuitry.
As a result of the increased device density of VLSI (Very-Large-Scale Integration) and ULSI (Ultra-Large-Scale Integration) integrated circuitry, wiring interconnective metallurgy between integrated circuit devices has become increasingly more complex. A higher packaging density likely requires an increase in the number of conductors, which likely reduces the space between adjacent conductors. Unfortunately, such dimensional reductions tend to increase the capacitance between adjacent conductors, thereby possibly increasing signal propagation delays and signal cross-talk. The limitations brought about by capacitive coupling between adjacent conductors has become a significant impediment to achieving higher wiring density.
The capacitive coupling effect is particularly apparent in high-density electronic packaging modules, such as three-dimensional multi-chip structures. In some multi-chip structures, the conductive leads on the integrated circuit chips are closely spaced, and adjacent leads may sometimes be separated by less than 1 micron. Consequently, reducing the distance between adjacent leads may adversely impact the functionality of the multi-chip structure due to an increase in the capacitive load between adjacent conductors. In addition, stacking the chips in close proximity to one another as required in multi-chip structures may also increase the capacitive coupling effect between conductors of adjacent chips.
Many integrated circuit chip designers have tried to address the problem of increased capacitive coupling between adjacent conductors by utilizing insulative materials that have lower dielectric constants than conventional dielectrics such as silicon-dioxide (SiO2), which has a dielectric constant of about 4.5. In some cases, polymers, such as polyimides, which have a dielectric constant of about 2.8-3.5, have been used in place of SiO2. However, the polyimides provide limited improvement for the capacitive coupling problem and, therefore, do not provide a significant advantage in use.
Alternatively, interconnects incorporating an air bridge structure have also been developed and are described in prior art references such as U.S. Pat. No. 5,891,797 to Farrar. Air bridge structures generally comprise suspended conductors that are surrounded by an air gap instead of the more conventional insulators. For example, U.S. Pat. No. 5,324,683 to Fitch et al. describes the formation of an air bridge structure in an integrated circuit by removing all or a portion of the dielectric layer between conductors so that the conductors are surrounded and insulated by an air gap. Air has a dielectric constant of approximately 1.0, which is substantially less than the dielectric constants of conventionally used insulators such as SiO2 or various polyimides. As such, the air-gap insulator provides some improvement for the capacitive coupling effect associated with the increased wiring density of integrated circuit chips.
Although air bridge structures facilitate the development of integrated circuits with higher wiring density, the use of air bridge structures introduces new manufacturing challenges such as protecting the suspended air bridge conductors from being damaged during fabrication. To address this concern, a temporary support material as disclosed in Applicant""s co-pending U.S. patent application Ser. No. 09/945,024, entitled MULTI-CHIP ELECTRONIC PACKAGE AND COOLING SYSTEM, which is hereby incorporated by reference in its entirety, can be used to stabilize and support the air bridges during fabrication. The temporary support material can be positioned beneath suspended air bridge conductors during manufacturing to provide rigidity to the conductors and subsequently removed when the chip stack assembly is complete. Disadvantageously, however, the temporary support material can impose certain constraints on in-process testing of the individual chip components and sub-assemblies.
In typical chip production, chips are tested at one or more points through a series of process steps with final functional testing of the individual chips being done prior to packaging. At many of these test points, chips such as memory chips are typically exercised at its rated speed and logic chips are tested for their speed and logic functions. Chips that pass the tests are usually packaged and subject to additional testing including margin tests for memory chips and more extensive functional tests for logic chips along with speed testing and sorting. With the higher speed sorts, generally, receiving a premium price in the market place. In some cases, if the chips are running at a relatively high yield, the final functional testing for chips may be delayed until after packaging, thus saving one testing cycle. For example, in the construction of large processors, memory chips with relatively high yield may be first assembled onto cards and these cards are then tested upon assembly. Additionally, a final system test is typically performed upon completion of assembling the entire system. Thus, the various testing steps allow defective chips to be detected and repaired or discarded at each step of the chip fabrication and assembly process.
However, the presence of the temporary support material in multi-chip structures may significantly increase the capacitive load on individual circuit elements thereby temporarily altering various functional properties of the integrated circuit devices. This temporary change in device characteristics caused by the support material makes it difficult to obtain accurate in-process device test results. Consequently, defective devices cannot be distinguished from the properly functioning ones during fabrication.
Hence, from the foregoing, it will be appreciated that there is a need for a method of performing accurate in-process testing of integrated circuit chips when the device properties are temporarily altered during the fabrication process. To this end, there is a particular need for a method of performing accurate in-process testing of a multi-chip electronic module comprising air bridge structures supported by a temporary material that affects the capacitive load of the circuit elements during fabrication.
In one aspect, the preferred embodiments of the present invention provide a method of manufacturing an integrated circuit chip, incorporating a novel in-process test sequence. The method comprises first forming a plurality of devices on a semiconductor substrate and then testing the device properties to determine if the devices are functional. Preferably, the testing is performed on special Kerf sites formed on the substrate. The method further comprises forming a plurality of conductors wherein at least some of the conductors are air bridge structures supported by a temporary member that may alter the device properties. In one embodiment, after formation of the conductors, the chip is subject to a chip metallurgy test performed on special Kerf test sites to determine whether the conductors are properly formed. The structures in the Kerf may include both active devices along with conductive structures which enable the testing of lines for resistivity from which the dimensions of the lines can be inferred. After the interconnects are formed, the process further comprises testing the devices at a speed substantially slower than the rated speed of the devices to determine whether proper electrically interconnections are established between devices. Preferably, the slow speed test is designed in a manner such that its results are substantially unaffected by the changes in device property brought about by the temporary member. After the device slow speed test, the process continues with completing formation of the chip, which can include assembling the chip into a chip stack to form a multi-chip module. After chip formation is complete, the temporary support material is removed and the chip is exercised at its rated speed to test the functionality of the chip.
In another aspect, the preferred embodiments of the present invention provide a method of forming a multi-chip electronic module. The method comprises forming a plurality of devices on a semiconductor substrate and testing the device properties to determine whether the devices are properly formed. The method continues with forming a support frame on an upper surface of the semiconductor substrate. Preferably, the support frame extends from the upper surface of the substrate and defines a protected spatial region for interconnection wiring. Preferably, the support frame also comprises a plurality of openings on a lateral surface of the support frame so as to permit a thermally conductive fluid to enter said spatial region and remove heat from the air bridge conductors and other interconnection wiring formed in the spatial region. In one embodiment, a temporary support material is also formed on the upper surface of the substrate in a manner such that the temporary support material stabilizes and provides structure support for the air bridge conductors so as to permit the chip to be processed and handled without causing damage to the air bridges and other interconnection. The temporary support material may comprise an insulative material that significantly increases the capacitive load of the devices and thus can alter device functional performances. To reduce the likelihood of generating erroneous test results based on altered device properties, the method further comprises exercising the devices at a speed substantially slower than the rated speeds of the devices to determine whether proper interconnections are made between the devices. Preferably, the devices are exercised at a speed that is sufficiently slow so that the test results are not impacted by the increase in capacitive load brought about by the temporary support material.
After slow speed testing the devices, the method further comprises assembling the semiconductor substrate in a chip stack in a manner such that an upper surface of the support frame is positioned adjacent to a lower surface of a second semiconductor substrate. At this stage, the chip stack is tested at a speed that is also substantially slower than its rated speed to determine whether the chips within the stack are properly interconnected to each other. The method follows with removal of the temporary support material after the chip stack assembly is complete. After removal of the temporary support material, the entire multi-chip module is exercised at its rated speed and run through a series of functional and connectivity tests to ensure that the system functions properly. In one embodiment, the method further comprises enclosing the chip stack inside an enclosure and introducing a thermally conductive fluid to the enclosure. The thermally conductive fluid has a thermal conductivity greater than that of air and the conductive fluid travels through the opening in the support frame and contacts the air bridge conductors formed in the spatial region and removes heat therefrom.
Advantageously, the preferred test sequence improves the yield of the final systems test because the test sequence provides a series of in-process tests that are designed to test various device properties and metallurgy of the integrated circuit before the circuit is incorporated into a system. Furthermore, the preferred test sequence provides tests that are modified to accommodate the incorporation of the temporary support material in the circuit structure during fabrication. The tests are modified in a manner such that the results are substantially unaffected by the increase in capacitive load brought about by the temporary support material. These and other advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.